As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin field-effect transistors (Fin FETs). In a Fin FET, the transistor channel rises above the planar substrate to form a fin structure, with a gate electrode adjacent to two side surfaces and the top surface of a channel region with a gate dielectric layer interposed between them.
Multi patterning may be used to pattern Fin FET gate electrodes (e.g., metals) in a process known as multi patterning gate (MPG) loop. The MPG loop is an important process for an advanced technology node, for example, N10 process flow. The MPG loop can damage the gate metal by undesirably reducing the gate height, which can adversely affect the device performance. Solutions are required that can effectively reduce the gate height reduction damage resulting from the MPG loop.